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nt 6611 1k 4-bit microcontroller with lcd driver 1/22 ver 1.0 f eat u r es ! n t 6610c -based single-chip 4-bit microcontroller w i th lc d driv er ! r o m : 1024 16 bits ! r a m : 256 4 bits (data memory ) ! o peration voltage r ange: 2.2v - 5.4v (3v ty pically ) ! 16 c m o s i/o pins (po r t a - d , c m o s or o pen d r ain by code option ) ! 4 lev el subroutine nesting (including interrupts) ! t w o 8-bit timers w i th pre-div i der circuit ! o scillator w arm-up timer ! 4 priority interrupt sources: - ex ternal interrupt (falling edge) - t i m e r0 interrupt - t i m e r1 interrupt - portb interrupt (falling edge) ! c l ock source: 32.768kh z cry s tal or 262k r c (ty p e is programmable by code option) ! instr u ction cy cle time: 4/32.768kh z ( 122 s) for 32.768kh z cry s tal 4/262kh z ( 15 s) for 262kh z r c ! lc d driv er 4 26 (1/4 duty , 1/3 bias or 1/3 duty , 1/2 bias) ! t w o low pow er operation modes - h a lt or st o p mode ! built-in alarm generator (carrier frequency : 2kh z or 4kh z code option) ! low pow er consumption (iop < 10 a, 32.768kh z , 3v) ! bonding option for multi-code softw are ! av ailable in c h i p fo r m g e n e ral descrip t i o n n t 6611 is a single-chip microcontroller integrated w i th an n t 6610c c p u core, sr am , timer, alarm generator, lc d driv er, i/o port, and program r o m . p a d configur a t ion NT6611 s e g 1 8 seg15 12 34 52 51 49 47 67 8 91 0 11 12 38 37 36 35 34 33 32 31 30 29 28 27 26 25 45 46 48 17 13 14 15 16 50 18 19 20 24 23 39 40 41 42 43 44 22 s e g 1 9 s e g 2 0 s e g 2 1 s e g 2 2 s e g 2 3 s e g 2 4 s e g 2 5 s e g 2 6 c o m 1 c o m 2 s e g 1 s e g 1 7 s e g 2 t e s t r e s e t v d d p o r t a 0 p o r t a 1 p o r t a 2 p o r t a 3 p o r t b 0 p o r t b 1 p o r t b 2 seg14 seg13 seg12 seg16 seg10 seg9 seg8 seg7 seg11 seg5 seg4 seg3 portb3 seg6 portc0 portc1 portc2 portc3 portd0 portd1 portd2 portd3 gnd osco osci com4 com3 21 b1 5 b0 http://
NT6611 2/22 ver 1.0 blo ck diag ram cpu core ram (256 x 4 ) 8-bit timer (2) i/o ports (3*4) lcd ram common drivers segment drivers cpu operating voltage & lcd voltage divider portb, portc portd com1 - com4 seg1 - seg26 test gnd reset osci osco rom (1024 x 16) porta or extemal int porta.0 (int) osc alarm porta.1(bd) porta.2 (bd) generator porta.3 pad descrip t i o n pad n o. d esignation i/o d escr iption 2 - 1, 52 - 29 seg 1 - 26 o s egment signal output for lc d display . seg1 - 4 as output 3 t est i test pin internally pull-down ( no connect for user) 4 reset i p ad reset input 5v dd p power pin 5 b 0 i bonding option, internally pull-low 6 - 9 p o r t a 0 - 3 i/o bit programmable i/o pa.0 could be ex ternal interrupt input( int ) pa.1, pa.2 could be buzzer output pa.1 (bd), pa.2 ( bd ) 10 - 13 po r t b0 - 3 i/o bit programmable i/o, vector interrupt (active falling edge) 14 - 17 po r t c 0 - 3 i/o bit programmable i/o 18 - 21 po r t d 0 - 3 i/o bit programmable i/o 22 g n d p ground pin 22 b1 i bonding option, internally pull-high 23 o s c o o oscillator output pin, connected to crystal oscillator 24 o s c i i oscillator input pin, connected to crystal or external resistor 28 - 25 c o m 1 - 4 o common signal output for lcd display total 52 pads for mask type.
NT6611 3/22 ver 1.0 functional description cpu t he c p u contains the follow i ng functional blocks: p r ogram c ounter, a r ithmetic logic u nit (a lu ), c arry flag, a ccumulator, table b r anch r egister, d a ta p o inter (in x , d p h , d p m , and d p l), and s t acks. rom t he r o m can address 1024 w o rds 16 bits of program area from $000 to $3ff. t here is an area from address $0 through $4 that is reserv ed for special interrupt serv ice routines, such as starting at v e ctor address. a ddr ess instr u ction r emar ks 000h jm p instruction jump to reset service routine 001h jmp instruction jump to external interrupt service routine 002h jmp instruction jump to timer0 service routine 003h jmp instruction jump to timer1 service routine 004h jmp instruction jump to pb service routine (portb) * j m p instruction can be replaced by any instruction. ra m built-in r a m contains of general purpose data memory , lc d r a m , and sy stem register. d a ta memory , lc d r a m , and sy stem register can be accessed by direct addressing in one instruction. t he follow i ng is the memory allocation map: $000 - $01f: sy stem register and i/o $020 - $11f: d a ta memory (256 4 bits, div i ded into 2 banks). $300 - $319: lc d ram space (26 4 bits).
NT6611 4/22 ver 1.0 t he configuration of sy stem register: bit 3 b it 2 b it 1 b it 0 r /w remarks $00 iex i et 0 i et 1 i ep r / w interrupt enable flags $01 ir q x ir q t 0 i r q t 1 ir q p r / w interrupt request flags $02 - t 0m .2 t 0 m . 1 t 0m .0 r / w bit0-2: timer0 mode register $03 - t 1m .2 t 1 m . 1 t 1m .0 r / w bit0-2: timer1 mode register $04 t 0l.3 t 0l.2 t 0l.1 t 0l.0 r /w timer0 load/counter register low nibble $05 t 0 h . 3 t 0h .2 t 0 h . 1 t 0h .0 r / w timer0 load/counter register high nibble $06 t 1l.3 t 1l.2 t 1l.1 t 1l.0 r /w timer1 load/counter register low nibble $07 t 1 h . 3 t 1h .2 t 1 h . 1 t 1h .0 r / w timer1 load/counter register high nibble $08 pa.3 pa.2 pa.1 pa.0 r /w porta $09 pb.3 pb.2 pb.1 pb.0 r /w portb $0a pc.3 pc.2 pc.1 pc.0 r/w portc $0b pd.3 pd.2 pd.1 pd.0 r/w portd $ 0 c ---- -reserved $0d - - b1 b0 r bonding option $0e t b r . 3 t br .2 t b r . 1 t br .0 r / w table branch register $0f in x . 3 i n x .2 in x . 1 i n x .0 r / w pseudo index register $10 d p l.3 d pl.2 d p l.1 d pl.0 r / w data pointer for inx low nibble $11 - d pm .2 d p m . 1 d pm .0 r / w data pointer for inx middle nibble $12 - d ph .2 d p h . 1 d ph .0 r / w data pointer for inx high nibble $13 o / s l c d o ff h l m pam r / w b it0: set pa.1, pa.2 as alarm o / p bit1: heavy load m ode bit2: lcd off bit3: set lcd segment as outport $14 aec 3 aec 2 aec 1 aec 0 r /w alarm envelope control $15 - - - d u t y r /w bit0: change lcd duty to 1/4 duty, 1/3 bias $16 ~ $1f ---- - r e s e r v e d
NT6611 5/22 ver 1.0 sy stem r egister 0d h bit 3 bit 2 bit 1 bit 0 r/w remarks power-on $0d h - - b 1 b 0 r bit0: bonding option 0, internal w eak driv e bit1: bonding option 1, internal w eak driv e pull low pull high xx10 yes x x 0 0 b1 bond to gnd x x 1 1 b0 bond to v dd x x 0 1 b1 bond to gnd and b0 bond to v dd gnd gnd v dd b0 b1 gnd v dd b0 b1 gnd v dd b0 b1 v dd b0 b1 b1 = 1 b0 = 1 b1 = 0 b0 = 1 pcb b1 = 0 b0 = 0 NT6611 bonding option pcb b1 = 1 b0 = 0 u p to 4 different bonding options are possible for the user' s needs. t he chip' s program has 4 different program flow s that w ill v a ry depending on w h ich bonding option is used. t he readable contents of b1 and b0 w ill differ depending on bonding.
NT6611 6/22 ver 1.0 sy stem r egister 13 bit 3 bit 2 bit 1 bit 0 r/w remarks power on 13 o / s l c d o ff h l m pam r / w b it0: set pa.1, pa.2 as alar m output bit1: heav y load mode bit2: lcd pow e r control bit3: set seg1 - 4 as output ports x x x 0 porta.1, porta.2 as i/o port yes x x x 1 porta.1, porta.2 as alarm output x x 0 x no heavy load yes x x 1 x heavy load mode x 0 x x lcd signal on yes x 1 x x lcd signal off 0 x x x seg1 - 4 as lcd output yes 1 x x x seg1 - 4 as output ports heavy lo ad m ode (hlm ): t h is mode is designed for the 32khz cry s tal oscillator, so that the oscillation can be maintained in a noisy pow er env ironment. t he pow er might drop suddenly w hen the alar m is driv ing a speaker. t he h lm is designed to control this pow er v a riation. t he consumption of pow er w ill increase during the use of the h l m mode, but it w ill not affect the r c oscillator. note : t he h lm needs about 5 instruction cy cles to set-up the oscillation for 32.768kh z cry s tal oscillator.
NT6611 7/22 ver 1.0 sy stem r egister 14, aec : bit 3 bit 2 bit 1 bit 0 r/w remarks power on $14 aec3 aec2 aec1 aec0 r/w alarm envelope control 0000 dc envelope yes x x x 1 1hz envelope x x 1 x 2hz envelope x 1 x x 4hz envelope 1 x x x 8hz envelope d e fault carrier frequency is 4kh z . c an be selected to 2kh z by code option. w r it e mode: control the env elop selection. r ead mode can read out current env elope w a v e forms. below is the alar m functional block equiv a lent circuit diagram. t o activ a te the alar m function, first sw itch the pam to alar m o u t p u t mode. after setting pam equal to 1, then set the proper env elope. w hen the data w r ites into aec , the env elope counter w ill be sy nchroniz ed at the same time. t he programmer can read back the env elope from aec register and make any pattern changes needed by programmer. the read operation will not affect the alarm output waveform. /4 16hz 8hz 4hz 2hz 1hz rd $14 to sound mixer wr $14 mask option mask option 4k or 2k osco osci 1 2 4 7 3 6 8 9 10 11 rrrrr 32k or 262k the programming alarm waveform is shown below: 1h z 2h z 4h z 8h z 16h z aec = $0 pam = 1 aec = $8 pam = 1 aec = $c pam = 1 bd output 2k or 4k aec = $a pam = 1 aec = $f pam = 1
NT6611 8/22 ver 1.0 sy stem r egister 15 bit 3 bit 2 bit 1 bit 0 r/w description power on $15 - - - duty r/w bit0: lcd duty control. - - - 1 lcd driver = 1/4 duty, 1/3 bias - - - 0 lcd driver = 1/3 duty, 1/2 bias yes lcd driv e r t he lc d driv er contains a controller, v o ltage generator, 4 common signal pins, and 26 segment driv er pins. t here are tw o different driv ing modes that are programmable, one is 1/4 duty and 1/3 bias, the other is 1/3 duty and 1/2 bias. d r i vin g mode is controlled by register 15 and the pow er-on status is 1/3 duty , 1/2 bias. t he controller consists of display data r a m and a duty generator. t he lc d data r a m is a dual port r a m that transfers data to segment pins automatically w i thout a program control. lc d segment 1 - 4 can also be used as output ports, it is selected by the bit3 of sy stem register 13. w hen segments 1 - 4 are output ports, data can be w r itten to bit 0 of the same address (300h - 303h ). lc d r a m can be used as data memory if needed. w hen the "st o p" instruction is ex ecuted, the lc d w ill be turned off, but the data of lc d r a m is the same before ex ecution the "st o p" instruction. c onfiguration of lc d ra m area: (1) w hen segments 1 - 4 are used as output ports: a ddress bit 3 b it 2 b it 1 b it 0 com 4 com 3 com 2 com1 300h - - - d at a_bit 301h - - - d at a_bit 302h - - - d at a_bit 303h - - - d at a_bit (2) w hen segments 1 - 4 are used as segment outputs: a ddress bit 3 b it 2 b it 1 bit 0 com 4 com 3 com 2 com1 300h seg 1 seg 1 seg 1 seg1 301h seg 2 seg 2 seg 2 seg2 302h seg 3 seg 3 seg 3 seg3 303h seg 4 seg 4 seg 4 seg4
NT6611 9/22 ver 1.0 (3) segments 5 - 26 address bit 3 bit 2 bit 1 bit 0 address bit 3 bit 2 bit 1 bit 0 com4 com3 com2 com1 com4 com3 com2 com1 304h seg5 seg5 seg5 seg5 30fh seg16 seg16 seg16 seg16 305h seg6 seg6 seg6 seg6 310h seg17 seg17 seg17 seg17 306h seg7 seg7 seg7 seg7 311h seg18 seg18 seg18 seg18 307h seg8 seg8 seg8 seg8 312h seg19 seg19 seg19 seg19 308h seg9 seg9 seg9 seg9 313h seg20 seg20 seg20 seg20 309h seg10 seg10 seg10 seg10 314h seg21 seg21 seg21 seg21 30ah seg11 seg11 seg11 seg11 315h seg22 seg22 seg22 seg22 30bh seg12 seg12 seg12 seg12 316h seg23 seg23 seg23 seg23 30ch seg13 seg13 seg13 seg13 317h seg24 seg24 seg24 seg24 30dh seg14 seg14 seg14 seg14 318h seg25 seg25 seg25 seg25 30eh seg15 seg15 seg15 seg15 319h seg26 seg26 seg26 seg26 i/o port n t 6611 has 16 c m o s quasi-i/o ports, po r t a, po r t b, po r t c , po r t d . all i/o ports are bit programmable. port a, b, c, d if porta,b,c,d are pull-high internally, it is weak drive. the equivalent circuit is below: data-in data-out i/o pad timer n t 6611 has tw o 8-bit timers. t heir operation is counting-up. the timers consist of an 8-bit counter and an 8-bit preload register. pre-scaler sync tosc 8-bit counter t0m f osc /4 t he timers prov ide the follow i ng functions: - programmable interv al timer function. - r ead counter v a lue. timer0 and timer1 configuration and o p eration both the t i mer0 and t i mer1 consists of an 8-bit w r ite-only timer load register (t l0l, t l 0h ; t l1l, t l1h ), and an 8-bit read-only timer counter (t c 0l, t c 0h ; t c 1l, t c 1h ). each of them has low order digits and high order digits. t h e timer counter can be initializ ed by w r iting data into the timer load register (t l0l, t l0h ; t l1l, t l1h ). t he low - order digit should be w r itten first, and then the high-order digit. t he timer counter is loaded w i th contents of the load register automatically w h en the high order digit is w r itten or counts ov erflow happen. t he timer ov erflow w ill generate an interrupt if the interrupt enable flag is set. t he timer can be programmed in sev eral different sy stem clock sour ces by setting the t imer m o de r e gister ( t m0 , t m1 ) . t i mer load r egister: since the register h controls the phy sical r ead and w r it e operations, please follow these steps: w r ite o peration: low nibble first; h i gh nibble to update the counter r ead o peration: h i gh n i bble first; low nibble follow ed. t i mer m ode r egister
NT6611 10/22 ver 1.0 load reg. h 8-bit timer counter load reg. l latch reg. l t he 8-bit counter counts prescaler ov erflow output pulses. t he t i mer m ode registers (t m 0 , t m 1) are 4-bit registers used for the timer control as show n in table1 and table 2. t hese mode registers select the input pulse sources into the timer. table 1: timer 0 mode r e gister ($02) tm0.2 t m0.1 tm0.0 p r escaler d i v i de r a tio clock source 000 / 2 11 system clock 001 / 2 9 system clock 010 / 2 7 system clock 011 / 2 5 system clock 100 / 2 3 system clock 101 / 2 2 system clock 110 / 2 1 system clock 111 / 2 0 system clock table 2: timer 1 mode r e gister ($03) tm1.2 t m1.1 tm1.0 p r escaler d i v i de r a tio clock source 000 / 2 11 system clock 001 / 2 9 system clock 010 / 2 7 system clock 011 / 2 5 system clock 100 / 2 3 system clock 101 / 2 2 system clock 110 / 2 1 system clock 0 system clock
NT6611 11/22 ver 1.0 interrupt four interrupt sources are av ailable on n t 6611: external interrupt ( in t share w i th pa.0) t i m e r0 interrupt t i m e r1 interrupt port?s falling edge detection interrupt ( pb ) t he configuration of sy stem register $00: bit 3 bit 2 bit 1 bit 0 r/w remark $00 iex iet0 iet1 iep r/w interrupt enable flags external interrupt ( int ) ex ternal interrupt is shared w i th the bit0 of po r t a. w hen bit3 of sy stem register 0(iex ) is set to 1, the ex ternal interrupt w i ll be enabled, and a falling edge signal on pa.0 w ill generate an ex ternal interrupt. (n ote: w h ile ex ternal interrupt is enabled, w r i ting a ?0? to bit0 of po r t a w ill generate an ex ternal interrupt). t i mer0, t i mer1 interrupt, port interrupt and i/o ports t he input clock of t i mer0 and t i mer1 are based on o s c clock. t he programming of t i mer interrupt, port interrupt and i/o ports refer to n t 6610c spec. " interrupt servicing sequence diagram: instruction execution i1 instruction execution i2 fetch vector address reset ie.x interrupt generated interrupt accepted start at vector address instruction execution n vector generated stacking inst. cycle 1 2 3 4 5 interrupt n e sting: during the nt 6610c cpu interrupt s e rv ic e, the us er c an enable any int e rrupt enable flag before returning from the interrupt. t he serv icing sequence diagram show s the nex t interrupt and the nex t nesting interrupt occurrences. if the interrupt request is ready and the instruction of ex ecution n is ie enable, then the interrupt w ill start immediately after the nex t tw o instruction ex ecutions. h o w e v e r, if instruction i1 or instruction i2 disables the interrupt request or enable flag, then the in terrupt serv ice w ill be terminated. sy stem c lock n t 6611 has one clock source. o s c 1 is 32.768kh z cry s tal or 262kh z r c determined by code option. t he o s c generates the basic clock pulses that prov ide the sy stem clock to supply c p u and on-chip peripherals (t im er 0, t i m e r 1, lc d ) .
NT6611 ver 1.0 12/22 in st ru ct io n s all instructions are one cy cle and one w ord instructions. t he characteristics is memory oriented operation. arithmetic and logical instruction a ccumulator t y pe mnemonic instruction code function flag change ad c x ( ,b) 00000 0bbb xxx xxxx ac mx + ac + cy cy ad c m x ( ,b) 00000 1bbb xxx xxxx ac,m x mx + ac + cy cy ad d x ( ,b) 00001 0bbb xxx xxxx ac mx + ac cy ad d m x ( ,b) 00001 1bbb xxx xxxx ac,m x mx + ac cy sbc x ( ,b) 00010 0bbb xxx xxxx ac mx + -ac + cy cy sbc m x ( ,b) 00010 1bbb xxx xxxx ac,m x mx + -ac + cy cy su b x ( ,b) 00011 0bbb xxx xxxx ac mx + -ac + 1 cy su bm x ( ,b) 00011 1bbb xxx xxxx ac,m x mx + -ac +1 cy eo r x ( ,b) 00100 0bbb xxx xxxx ac mx ac eo r m x ( ,b) 00100 1bbb xxx xxxx ac,m x mx ac o r x ( ,b) 00101 0bbb xxx xxxx ac mx | ac o r m x ( ,b) 00101 1bbb xxx xxxx ac,m x mx | ac an d x ( ,b) 00110 0bbb xxx xxxx ac mx & ac an d m x ( ,b) 00110 1bbb xxx xxxx ac,m x mx & ac sh r 11110 0000 000 0000 0 ac[3]; ac[0] cy ; ac shift right one bit cy immediate t y pe mnemonic instruction code function flag change ad i x , i 01000 iiii xxx xxxx ac mx + i cy ad im x , i 01001 iiii xxx xxxx ac,m x mx + i cy sbi x , i 01010 iiii xxx xxxx ac mx + -i +1 cy sbim x , i 01011 iiii xxx xxxx ac,m x mx + -i + 1 cy eo r i m x , i 01100 iiii xxx xxxx ac,m x mx i o r im x , i 01101 iiii xxx xxxx ac,m x mx | i an d i m x , i 01110 iiii xxx xxxx ac,m x mx & i * i n the assembler asm 66 v1.0, eo r i m memonic is eo r i. h o w e v e r, eo r i has the same operation identical w i th eo r i m . same for the o r im w i th respect to o r i, and an d i m w i th respect to an d i . d e cimal adjust mnemonic instruction code function flag change d aa x 11001 0110 xxx xxxx ac;m x decimal adjust for add. cy d as x 11001 1010 xxx xxxx ac;m x decimal adjust for sub. cy
NT6611 ver 1.0 13/22 t r ansfer instruction mnemonic instruction code function flag change ld a x ( ,b) 00111 0bbb xxx xxxx ac mx st a x ( ,b) 00111 1bbb xxx xxxx m x ac ld i x , i 01111 iiii xxx xxxx ac,m x i control ins t ruc t ion mnemonic instruction code function flag change baz x 10010 xxxx xxx xxxx pc x if ac=0 bnz x 10000 xxxx xxx xxxx pc x if ac 0 bc x 10011 xxxx xxx xxxx pc x if cy=1 bnc x 10001 xxxx xxx xxxx pc x if cy 1 ba0 x 10100 xxxx xxx xxxx pc x if ac(0)=1 ba1 x 10101 xxxx xxx xxxx pc x if ac(1)=1 ba2 x 10110 xxxx xxx xxxx pc x if ac(2)=1 ba3 x 10111 xxxx xxx xxxx pc x if ac(3)=1 c a ll x 11000 xxxx xxx xxxx st cy ; pc +1 pc x(not include p) rtnw h;l 11010 000h hhh llll pc st; tbr hhhh; a llll rtni 11010 1000 000 0000 cy ;pc st cy halt 11011 0000 000 0000 stop 11011 1000 000 0000 jm p x 1110p xxxx xxx xxxx pc x(include p) t j m p 11110 1111 111 1111 pc (pc11-pc8) (tbr) (a) n o p 11111 1111 111 1111 no operation w here, pc program counter i immediate data ac ac c u m u lator logical exclusive or -ac c omplement of accumulator | logical or c y c a rry flag & logical and m x d ata memory bbb r a m bank=000 p rom page =0 st stack t br t able branch r egister
NT6611 ver 1.0 14/22 a b so lu t e m aximu m rat i n g s * d c supply voltage . . . . . . . . . . . . . . . . . . -0.3v to +5.5v input voltage. . . . . . . . . . . . . . . . . . . . . . . -0.3v to v dd +0.3v o perating ambient t e mperature . . . . . . . . 0 c to +60 c storage t e mperature . . . . . . . . . . . . . . . -55 c to +125 c * c omments stresses abov e those listed under "absolute m ax i mum r a tings" may cause permanent damage to this dev i ce. t hese are stress ratings only . functional operation of this dev ice at these or any other conditions abov e those indicated in the operational sections of this specification is not implied or intended. ex posed to the absolute max i mum rating conditions for ex tended periods may affect dev ice reliability . dc elect rical ch aract erist i cs (v dd = 3.0v, g n d = 0v, t a = 25 c, f os c = 32.768kh z , unless otherw i se specified) parameter s y m bol min. ty p. max. unit conditions operating voltage v dd 2.2 3 3.4 v o perating c u rrent i op 51 0 a all output pins unload ex ecute n o p instruction standby c u rrent i sb1 1.5 2 .5 a all output pins unload (h alt mode) ex clude lc d current standby c u rrent i sb2 1 a all output pins unload (st o p mode) lc d off, no current input high voltage v ih 0.7 v dd v dd + 0.3 v porta, portb, portc, portd input low voltage v il gnd - 0.3 0.2 v dd v porta, portb, portc, portd o u tput h i gh voltage v oh1 2.3 v port a, port b, port c (i oh = 15 a) o u tput low voltage v ol1 0.2 v port a, port b, port c (i ol = 300 a) output high voltage v oh2 2.1 v bd/ bd (set pa.1and pa.2 to be alarm output ), i oh = 2ma output low voltage v ol2 0.9 v bd/ bd (set pa.1and pa.2 to be alarm output ), i ol = 2ma o u tput h i gh voltage v oh3 2.8 v segx , i oh = 3 a , seg 1 - 4 to be output port (for reference only ) o u tput low voltage v ol3 0.2 v segx , i ol = 3 a , seg 1 - 4 to be output port (for reference only ) o u tput h i gh voltage v oh4 2.8 v com x , i oh = 8 a (for reference only ) o u tput low voltage v ol4 0.2 v com x , i ol = 8 a (for reference only ) lc d lighting i lc d 6.5 7 .5 a h a lt mode
NT6611 ver 1.0 15/22 dc elect rical ch aract erist i cs (v dd = 5.0v, g n d = 0v, t a = 25 c, f os c = 32.768kh z , unless otherw i se specified) parameter symbol min. typ. max. unit conditions o perating voltage v dd 4.5 5 .0 5.4 v port a, port b, port c (i oh = 15 a) o perating voltage i op 15 30 a p ort a , port b, port c (i ol = 300 a) standby c u rrent i sb1 4.5 7 .5 a bd/ bd (set pa.1 and pa.2 to be alarm output ), i oh = 2ma standby c u rrent i sb2 1 a all output pins unload (st o p mode) lc d off, no current input high voltage v ih 0.7 v dd v dd + 0.3 v porta, portb, portc, portd input low voltage v il gnd - 0.3 0.2 v dd v porta, portb, portc, portd o u tput h i gh voltage v oh1 4.3 v segx , i oh = 3 a , seg 1 - 4 to be output port (for reference only ) o u tput low voltage v ol1 0.3 v segx , i ol = 3 a , seg 1 - 4 to be output port (for reference only ) o u tput h i gh voltage v oh2 4.1 v com x , i oh = 8 a (for reference only ) o u tput low voltage v ol2 1.0 v com x , i ol = 8 a (for reference only ) output low voltage v oh3 4.8 output low voltage v ol3 0.3 output low voltage v oh4 4.8 output low voltage v ol4 0.3 lc d lighting i lc d 19.5 2 3 a h a lt mode note : 1. o peration frequency v s . i sb1 i sb1 x = (frequency / 32.768kh z ) i sb1 0.8 2. o peration frequency v s . i op i opx = (frequency / 32.768kh z ) i op 0.8 3. h l m v s . iop, i sb1 and i sb2 if hlm = 1, i opx = i op 2, i sb1x = i sb1 2, i sb2x = i sb1 2
NT6611 ver 1.0 16/22 a c ch aract erist i cs (v dd = 3.0v, g n d = 0v, t a = 25 c, f os c = 32.768kh z , unless otherw i se specified) parameter symbol min. typ. max. unit conditions oscillation start time t stt 25 s halt time t htt 0si dd reduces to isb1 after instruction executing stop time t spt 0si dd reduces to isb2 after instruction executing frequency stability ? f/f 1 ppm [f(3.0)-f(2.4)]/f(3.0), crystal oscillator (for reference only) frequency variation ? f/f 10 ppm c1 = 5 - 25p (for reference only) a c ch aract erist i cs (v dd = 3.0v, g n d = 0v, t a = 25 c, f os c = 262kh z , unless otherw i se specified) parameter symbol min. typ. max. unit conditions oscillation start time t stt 2ms halt time t htt 0si dd reduces to isb1 after instruction executing stop time t spt 0si dd reduces to isb3 after instruction executing frequency stability ?? f ? /f 10 % ? f(3.0)-f(2.4) ? /f(3.0), rc oscillator (for reference only) frequency variation ?? f ? /f 15 % variation caused by process variation (for reference only)
NT6611 ver 1.0 17/22 t i ming wa v e for m 1/4 duty, 1/3 bias lcd waveform select unselect comx light unlight segx segn 3.9ms 15.625ms v dd3 com4 - segn segn+1 gnd com4 com3 com2 com1 com4 com3 com2 com1 v dd2 v dd1 v dd3 gnd v dd2 v dd1 v dd3 gnd v dd2 v dd1 v dd3 gnd v dd2 v dd1 v dd3 gnd v dd2 v dd1 v dd3 gnd v dd2 v dd1 v dd3 gnd v dd2 v dd1 -v dd3 -v dd2 -v dd1 segn+1 segn
NT6611 ver 1.0 18/22 1/3 duty, 1/2 bias lcd waveform select unselect com light unlight seg com1 com2 com3 com4 segn com3 com2 com1 segn+1 segn 3.9ms segn+1 11.7ms com1 - segn segn+2 v dd2 gnd v dd1 v dd2 gnd v dd1 v dd2 gnd v dd1 v dd2 gnd v dd1 v dd2 gnd v dd1 v dd2 gnd v dd1 v dd2 gnd v dd1 -v dd2 -v dd1 hl m w a ve fo rm hlm 1 0 heavy load on off 1ms or more
NT6611 ver 1.0 19/22 a pplic a t ion cir c uits ( f or r e f e r enc e only ) n t 6611 chip substrate connects to sy stem ground. ap 1 o s c : r c : 262k (code option) lc d panel: 1/4 duty , 1/3 bias; (s/w select 1/4 duty , auto 1/3 bias) lc d panel: 1/3 duty , 1/3 bias; (s/w select 1/4 duty , auto 1/3 bias; ignore duty 4 segments) porta - d : i/o osci 4 x 26 or 3 x 26 lcd 1/3 bias reset v dd gnd test porta - d 750k ? 0 - 50k v dd NT6611 ap 2 o s c : 32.768kh z cry s tal (code option) lc d : 1/3 duty , 1/2 bias port b - d: i/o po r t a.0: ex ternal interrupt porta.1, porta.2: alarm output (carrier frequency: 2khz or 4khz code option) (code option) osci 3 x 26 lcd 1/2 bias osco 32768hz buzzer porta.1 porta.2 porta.0 reset gnd test 20p 0 - 50k v dd NT6611
NT6611 ver 1.0 20/22 a pplic a t ion cir c uits (c ontinue d) ap 3 o s c : 32.768kh z lc d : 1/3 duty , 1/2 bias po r t b.1 = o u tput when v dd is higher than v lcd , reducing v dd tov dd1 can regulate the voltage. osci 3 x 26 lcd 1/2 bias osco 32768hz reset gnd test 20p 0 - 50k portb.1 v dd1 v dd v dd v dd1 v dd NT6611
NT6611 ver 1.0 21/22 bonding diagram s e g 1 8 seg15 1234 52 51 49 47 678 91 0 11 12 38 37 36 35 34 33 32 31 30 29 28 27 26 25 45 46 48 17 13 14 15 16 50 18 19 20 24 23 39 40 41 42 43 44 22 s e g 1 9 s e g 2 0 s e g 2 1 s e g 2 2 s e g 2 3 s e g 2 4 s e g 2 5 s e g 2 6 c o m 1 c o m 2 s e g 1 s e g 1 7 s e g 2 t e s t r e s e t v d d p o r t a 0 p o r t a 1 p o r t a 2 p o r t a 3 p o r t b 0 p o r t b 1 p o r t b 2 seg14 seg13 seg12 seg16 seg10 seg9 seg8 seg7 seg11 seg5 seg4 seg3 portb3 seg6 portc0 portc1 portc2 portc3 portd0 portd1 portd2 portd3 gnd osco osci com4 com3 NT6611 (0, 0) 21 b1 y x 5 b0 1750 m 1790 m * substrate connects to g n d . t he bonding w i re w i th diameter of 1.0mil is recommended. unit: m pad no. d esignation x y 1 seg 2 - 627 -770 2 seg 1 - 517 -770 3 t est -407 -770 4 reset -297 -770 5v dd -164 -770 b0 -i64 -673 6 p o r t a 0 - 54 -770 7 p o r t a 1 55 - 770 8 p o r t a 2 165 -770 9 p o r t a 3 275 -770 10 po r t b0 385 -770 11 po r t b1 505 -770 12 po r t b2 625 -770 13 po r t b3 749 -768 14 po r t c 0 747 -650 15 po r t c 1 747 -530 16 po r t c 2 747 -421 17 po r t c 3 747 -309 18 po r t d 0 747 -200 19 po r t d 1 747 -90 20 po r t d 2 747 19 21 po r t d 3 747 129 22 g n d 747 240 b1 747 309 23 o s c o 747 419 24 o s c i 747 530 25 c o m 4 747 650 pad no. d esignation x y 26 c o m 3 747 770 27 c o m 2 625 770 28 c o m 1 505 770 29 seg 26 385 770 30 seg 25 275 770 31 seg 24 165 770 32 seg 23 55 770 33 seg 22 -54 7 70 34 seg 21 -164 770 35 seg 20 -274 770 36 seg 19 -392 770 37 seg 18 -515 770 38 seg 17 -625 770 39 seg 16 -747 770 40 seg 15 -747 641 41 seg 14 -747 513 42 seg 13 -747 385 43 seg 12 -747 275 44 seg 11 -747 165 45 seg 10 -747 55 46 seg 9 - 747 -55 47 seg 8 - 747 -165 48 seg 7 - 747 -275 49 seg 6 - 747 -385 50 seg 5 - 747 -513 51 seg 4 - 747 -641 52 seg 3 - 747 -770
NT6611 ver 1.0 22/22 or de r i ng infor m a t ion part no. package NT6611h chip form

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